|Seminar om System Verilog
Advanced verification techniques with ModelSim DE – “ Questa Lite” Built around the stable base of the worlds most popular simulator, ModelSim; the new Deluxe Edition allows the user to take the first steps into advanced verification techniques. ModelSim DE gives you access to Code Coverage and Assertions and supports both SVA and PSL. This session will introduce these new capabilities as well as highlighting how use these to improve the thoroughness of your design verification.
SytemVerilog Assertions Assertions provide a dual functionality. They can monitor desired design functionality and verify that this is thoroughly tested OR they can define undesired functionality and flag if the design ever goes outside its intended range of operations. These both identify the capability of the design and its test bench and facilitate easier design reuse, both of which are areas essential to today’s design teams. This session will teach you the basics of Assertion Based Verification and start you on SVA (the main elements of which can also be applied to PSL as well).