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26. januar 2010

Seminar om System Verilog

Advanced verification techniques with ModelSim DE – Questa Lite” Built around the stable base of the worlds most popular simulator, ModelSim; the new Deluxe Edition allows the user to take the first steps into advanced verification techniques. ModelSim DE gives you access to Code Coverage and Assertions and supports both SVA and PSL. This session will introduce these new capabilities as well as highlighting how use these to improve the thoroughness of your design verification.

SytemVerilog Assertions Assertions provide a dual functionality. They can monitor desired design functionality and verify that this is thoroughly tested OR they can define undesired functionality and flag if the design ever goes outside its intended range of operations. These both identify the capability of the design and its test bench and facilitate easier design reuse, both of which are areas essential to today’s design teams. This session will teach you the basics of Assertion Based Verification and start you on SVA (the main elements of which can also be applied to PSL as well).

Tid:

09.00 - 16.00

Sted:

Karlslunde Feriecenter, karlslunde Strandvej 87, 2690 Karlslunde
Pris: Gratis men tilmelding påkrævet af hensynt til forplejning

Tilmelding:

4615 4464 eller dyrbergdyrberg.dk

 

2.-3. februar 2010

FPGA Forum - Trondheim

 

To dage med forskellige seminarer om FPGA relaterede emner. Dette er samlingspunktet for Norges specialister på området.

Tid:

09.00-17.00

Sted:

Hotel Britania
Pris: check: www.fpga-forum.no

Tilmelding:

check: www.fpga-forum.no

 

 
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